1. Field of the Invention
The present invention relates to voltage level detection circuits, and more particularly to power supply voltage level detection circuits used in power-on-reset circuits.
2. State of the Art
Voltage level detection circuits are used in integrated circuit (IC) devices to detect when the power supply reaches a particular level upon powering up the device or when the power supply drops below a certain level during operation or powering down. In general, voltage level detector designs include a differential input device that functions to compare the power supply (i.e., VDD) to a supply independent reference voltage to determine when the power supply has reached a minimum voltage level.
Often times voltage level detectors are used in power-on-reset (POR) circuits. POR circuits are often used when powering up digital ICs. The POR provides a delayed reset signal to portions of the IC to set logic within the circuit to a known state upon start-up. Specifically, when powering up an integrated circuit, the power supply voltage is often ramped up to the intended full level of the power supply voltage instead of directly applying full power. During this time, the integrated circuit is in an intermediate state and any reset signal generated while the circuit is being powered up may appear to be at a digital level other than the intended reset digital level. Consequently, the reset signal is generally provided to the remainder of the integrated circuit a short delay time after the power supply voltage has been applied to the power supply ports. The POR circuit includes a voltage level detector portion which detects when the power supply voltage has reached a predetermined voltage level as it is being ramped to full power. The remaining POR circuitry extends the application of the reset signal for a given amount of time after the level detection portion indicates the power supply has reached the predetermined voltage level.
One of the main disadvantages of currently used voltage level detectors is that it is dependent on the rate at which the power supply is ramped and this dependency can result in erroneous level detection results. In addition, these circuits dissipate power during times when level detection is not required.
The present invention is an improved voltage level detector design which obviates the need for generating a reference voltage by eliminating the differential input of the level detector and which includes a power-down mode for reducing power consumption.